Comparative Benchmarking of Pulse Generation Techniques for Conventional Pulsed Latches
Description
To design and benchmark pulsed latch architectures for reducing power consumption while maintaining performance in digital systems.
Conventional edge-triggered flip-flops are current solutions; this project develops pulsed latches offering 88-93% power reduction and improved energy efficiency.
Practical use cases include pipelines, registers, memory structures, and applications in portable, high-density, IoT, automotive, and HPC.
Abstract
3 Acknowledgment 4
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