SCL 180nm: Low Power Standard Cell Design Hardening of RISC-V Pinaka Shakti Processor

Generate a verified physical design of the Pinaka Shakti processor as a baseline for evaluating a custom low-power standard cell library.

Improved upon a previous failed implementation at 80% utilization by reducing core utilization to 65% and addressing congestion issues.

Physical implementation of the Pinaka Shakti RV32IMAC processor for evaluation of a custom low-power standard cell library.

Generate a verified physical design of the Pinaka Shakti processor as a baseline for evaluating a custom low-power standard cell library.