Diffusion model for Non-Deterministic Delay Prediction and Synthetic Data Generation

To augment handling of complex circuit scaling tasks with minimum resources using ML in VLSI workflow.

Traditional methods are computationally expensive; conventional ML is deterministic. Project uses diffusion models to learn probability distributions.

Accelerating timing analysis, power estimation, placement optimization, timing prediction, design space exploration, synthetic data generation.

The exponentially increasing circuit complexity and the end of Moore’s law poses a challenge for scaling the chip industry and the VLSI design flow. Integration of ML models along with EDA show promising signs for future and remain an interested branch for study and exploration. The work presented in this report is an addition in that exploration. With the increasing complexity of modern VLSI systems, there is a growing need for machine learning-based techniques that can accelerate timing analysis while maintaining high prediction accuracy. The work begins with transistor-level circuit design and ELDO simulation of basic digital gates including inverter, NAND, and NOR circuits implemented in 65nm CMOS technology in Cadence Virtuoso. A systematic parameter sweep methodology was developed to explore the design space by varying operating temperature, supply voltage, load capacitance, and transistor dimensions. Through extensive ELDO simulations, a dataset containing 26,460 samples was generated with delay- related metrics including propagation delay, rise time, and fall time. A conditional diffusion model based on denoising diffusion probabilistic modeling (DDPM)[1] was implemented and trained using PyTorch. The developed model achieved excellent prediction performance, with R² scores exceeding 0.997 across all delay metrics. The report also presents a comprehensive characterization and comparative physical analysis of a Transmission-Gate D-Flip-Flop (TG-DFF) and a True Single-Phase Clock D-Flip-Flop (TSPC- DFF) designed at the 65nm technology node. A custom python driven automation script was used to extract precise timings. The eldo parameter sweep generated a 6-dimensional dataset encompassing over ~50,000 simulations across varying Voltage, Temperature, input slews, output loads, and NMOS/PMOS transistor widths. The analysis of the dataset revealed that power is reduced by ~62% in TSPC FFs. The diffusion model is further extended to generate synthetic data for training ML models. Ultimately, the work quantifies and addresses the most important aspect of data bottleneck of AIML in VLSI design.

=== Page 3 === 3 LIST OF CONTENTS Abstract ................................................................................................................... 2