Design and Analysis of 6T SRAM Memory Array in 65 nm Cadence Virtuoso
Description
Design and analyze a 6T SRAM memory array in 65 nm Cadence Virtuoso for low-power IoT memory.
Literature surveyed sensing, assist schemes, bitline differential, and low-power SRAM design directions in 65 nm technology.
Low-power memory for IoT devices.
Abstract
Design and analyze a 6T SRAM memory array in 65 nm Cadence Virtuoso for low-power IoT memory.
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