A Comparative Study of Latch-Type Sense Amplifier and Majority Logic-Based Latch Sense Amplifier

To compare latch-type and majority logic-based sense amplifiers focusing on offset voltage, robustness, delay, area, and energy.

Latch-type SAs are fast but sensitive to mismatch; Majority logic SAs are robust but have increased complexity, area, and delay.

SRAM read circuits, cache memory systems, low-voltage memory architectures, high-speed computing systems, AI accelerators.

This paper presents a comparative analysis of latch-type conventional sense amplifiers and majority-logic-basedsenseamplifiers, withaprimaryfocusoninput-referredoffsetvoltageand robustness under process variations. The study evaluates the performance differences between the conventional latch architecture and the majority logic-based design in terms of sensitivity to device mismatch and sensing reliability. Extensive post-layout Monte Carlo simulations are carried out in 180 nm CMOS technology to analyze the statistical behavior of offset voltage. The results demonstrate that the majority-logic-based sense amplifier exhibits improved offset tolerance, reducedmismatchsensitivity, andenhancedoverallrobustnesscomparedtothecon- ventionallatch-typesenseamplifier.