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This paper presents a comparative analysis of latch-type conventional sense amplifiers and majority-logic-basedsenseamplifiers,withaprimaryfocusoninput-referredoffsetvoltageand robustness under process variations. The study evaluates the performance differences between the conventional latch architecture and the majority logic-based design in terms of sensitivity to device mismatch and sensing reliability. Extensive post-layout Monte Carlo simulations are carried out in 180 nm CMOS technology to analyze the statistical behavior of offset voltage. The results demonstrate that the majority-logic-based sense amplifier exhibits improved offset tolerance,reducedmismatchsensitivity,andenhancedoverallrobustnesscomparedtothecon- ventionallatch-typesenseamplifier.

To propose alternative pathways for universities to enhance and accelerate the commercialization of innovations, maximizing social benefit.

—Processing-in-memory(PIM)architecturesbasedon resistive random access memory (ReRAM) are promising candi- dates to overcome the von Neumann bottleneck. While prior works have demonstrated functionally complete logic compu- tation using 2T2R and 3T2R architectures, they lack efficient supportforshiftandrotationoperations,whichareessentialfor cryptographic workloads. This work proposes SHIMP (Shift and Implication), a ReRAM-basedin-memorycomputingarchitecturethatintegrates implication logic with multidirectional and circular shift op- erations. The architecture introduces routing-level innovations and a dual bit-line design enabling parallel data movement. SimulationusingSkyWaterOpenPDKvalidatesthefunctionality, with ReRAM cells exhibiting HRS ∼3.1MΩ and LRS ∼10kΩ, yieldingaresistanceratioof∼310×.Comparedtopriordesigns, SHIMP enhances flexibility and enables efficient mapping of cryptographic primitives.

Senseamplifiersarerequiredinhigh-speedmemorysystemstodetectverysmalldifferential voltages with high accuracy and reliability. However, device mismatches and process varia- tions introduce input-referred offset voltage into the circuit, significantly degrading sensing performance in dynamic latch-based architectures, such as StrongARM sense amplifiers. As technologyscalesandparasiticpost-layouteffectsare introduced,theimpactofthesemismatch effectsgrowslinearlywithdevicesize. Thisworkpresentsapost-layoutcomparativeanalysisofmismatch-mitigationtechniquesfor StrongARMsenseamplifiersacrossbaseline,upsized,andmajority-logic-basedarchitectures. ThebaselineStrongARMsenseamplifierisfirstanalyzedtoevaluatetheimpactofmismatch- inducedoffset underMonte Carlosimulations. AnupsizedStrongARM implementationis then investigatedasaconventional,sizing-basedapproachtoimprovetransistormatching. Inaddition, aredundancy-driven,majority-logic-basedarchitectureemployingthreeparallelsensingpaths andvotingcircuitryisproposedtostatisticallysuppressmismatch-inducedsensingerrors. Datafrom completed MonteCarlosimulations indicate thatthenewarchitectureis themost robusttomismatchvariationamongthearchitecturessimulated. Thenewarchitecturereduces theoffsetstandarddeviationfrom11.191mVforaStrongARMto3.705mVinapost-layout scenario. Althoughthenewarchitectureaddsdelaysandsensingenergyduetoredundantsensing pathsandvotinglogic,itimprovessensingreliability. Itsignificantlyreducesoffsetvariability compared to traditional single-path sensing. The results presented in this paper demonstrate thatusingredundancyinthesensingpathisagoodalternativetoaggressivetransistorsizingfor mitigatingpost-layoutmismatchesinhigh-speedmemoryapplications.

In this project, we worked on improving our earlier gesture-to-text and speech system. The previous version was able to detect hand gestures and convert them into text and speech, but it had several limitations such as one-way communication, slow text formation, and limited interaction features. In the current phase, we extended the system by adding dual-hand detection, auto-suggestion, next- word prediction, speech-to-text support, air whiteboard functionality, dynamic gesture recognition, and abrowser-basedinterface. MediaPipewasusedforhandlandmarkdetection, whilelightweightlogicwas used for suggestions and motion-based gesture detection so that the system could still run on a normal laptop. We also focused on improving the project from a technical and evaluation point of view. Hardware testing, software testing, and performance observations were included to better understand where the system performs well and where it remains weak. During testing, static alphabet gestures were found to bemorereliablethandynamicgestures,whiledynamicgestureswerestillusefulforcontrol-typeactions. The final system is more interactive, more complete, and better documented than the earlier version. 1 === Page 3 === Contents Abstract 1

To design a reliable, accurate, and affordable 'Made in India' mercury-free blood pressure monitoring device, preserving clinical accuracy.

To present a comprehensive simulation-based study of ten distinct current mirror topologies in 65nm and 45nm CMOS technology.

To present a comprehensive simulation-based study and unified comparison of ten current mirror topologies in 65nm CMOS technology.

Design and analyze a 6T SRAM memory array in 65 nm Cadence Virtuoso for low-power IoT memory.

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The exponentially increasing circuit complexity and the end of Moore’s law poses a challenge for scaling the chip industry and the VLSI design flow. Integration of ML models along with EDA show promising signs for future and remain an interested branch for study and exploration. The work presented in this report is an addition in that exploration. With the increasing complexity of modern VLSI systems, there is a growing need for machine learning-based techniques that can accelerate timing analysis while maintaining high prediction accuracy. The work begins with transistor-level circuit design and ELDO simulation of basic digital gates including inverter, NAND, and NOR circuits implemented in 65nm CMOS technology in Cadence Virtuoso. A systematic parameter sweep methodology was developed to explore the design space by varying operating temperature, supply voltage, load capacitance, and transistor dimensions. Through extensive ELDO simulations, a dataset containing 26,460 samples was generated with delay- related metrics including propagation delay, rise time, and fall time. A conditional diffusion model based on denoising diffusion probabilistic modeling (DDPM)[1] was implemented and trained using PyTorch. The developed model achieved excellent prediction performance, with R² scores exceeding 0.997 across all delay metrics. The report also presents a comprehensive characterization and comparative physical analysis of a Transmission-Gate D-Flip-Flop (TG-DFF) and a True Single-Phase Clock D-Flip-Flop (TSPC- DFF) designed at the 65nm technology node. A custom python driven automation script was used to extract precise timings. The eldo parameter sweep generated a 6-dimensional dataset encompassing over ~50,000 simulations across varying Voltage, Temperature, input slews, output loads, and NMOS/PMOS transistor widths. The analysis of the dataset revealed that power is reduced by ~62% in TSPC FFs. The diffusion model is further extended to generate synthetic data for training ML models. Ultimately, the work quantifies and addresses the most important aspect of data bottleneck of AIML in VLSI design. === Page 3 === 3 LIST OF CONTENTS Abstract ................................................................................................................... 2

This report describes the hardware-focused portion of an FMCW (frequency-modulated continuous-wave) ultrasonic radar built for unmanned aerial vehicles. The wider group effort spans additional software and learning-based components; here the emphasis is on the analog frontend,printedcircuititeration,benchvalidation,andairframeintegration. Commercial ultrasonics for small UAVs are convenient, but fixed-tone time-of-flight mod- ules are prone to interference and crosstalk when several units operate nearby. The custom sensor instead chirps across roughly 35–45 kHz, digitizes the return on an STM32G071, and recovers range via spectral analysis. My work concentrated on stretching usable range by re- tuning amplification and filtering, laying out a second-generation board that separates transmit and receive paths more cleanly, benchmarking the custom head against a standard HC-SR04 on a fixed rig, mounting the assembly on a flying quadrotor with UART streaming to the flight controller, and keeping the analog chain healthy through a semester of repeated assembly, dis- assembly,anddemonstrationuse. The outcome is a flight-mounted prototype that held up under real conditions: measur- able improvement in interference behaviour relative tothe baseline sensor on the bench, stable UARTtelemetryinhovertests,andareceiverchainthatcouldberepairedandre-biasedquickly whenclassroomhandlingexposedweakspotsinprotectionandgrounding.